(1) Field of the Invention
The present invention relates to a novel combination nonvolatile memory and a novel embedded memory. The nonvolatile memory is comprised of three key memories: ROM (Read-Only-Memory), EEPROM (Electrically Erasable and Programmable Read Only Memory) and FLASH. The embedded memory is comprised of the combination of the above three nonvolatile memories, SRAM, CPU, and shared buses of data, address, and control signals.
(2) Description of the Prior Art
ROM data can only be altered at the manufacturing site by changing the costly photo mask sets, while both data of EEPROM and FLASH is allowed to be in-system flexibly changed at user's site at lower cost and faster throughput than ROM. The main differences in product specification requirements between FLASH and EEPROM are not the write scheme nor write speed but the write size and endurance cycles. Endurance cycle stands for the number of successful program and erase cycles when changing FLASH or EEPROM data. Write operation in the present invention means an erase is commonly performed first and then followed by a program operation.
For example, both Flash and EEPROM memories can perform on-chip erase and program operation without relying on an external high-voltage power supply. In other words, a single low-voltage VDD supply is sufficient for in-system data reprogramming for both memories. Typically, only two preferred erase schemes such as edge-FN tunneling or channel-FN tunneling are extensively employed in both FLASH and EEPROM memories. Traditionally the program schemes are more available than the erase schemes. Besides FN-tunneling, CHE (Channel-Hot-Electron) and SCHEI(Source-side Hot-Electron-Injection) are the dominant schemes for 1Tr-ETOX(Electrically-Tunneling-Oxide) and 1.5Tr split-gate flash memory respectively. The technology that uses FN-tunneling erase schemes includes 1Tr-NAND FLASH from Toshiba and Samsung, 1Tr-AND from Hitachi, 1Tr-Dinor from Mitsubishi, 1Tr-OR from Aplus and EEPROM of 2Tr-FLOTOX. The major product specification differences between FLASH and EEPROM are the write-size and P/E cycles. For example, FLASH typically only performs page (128 B) or block (64 KB) erase and page (128 B) or byte (1 B) program, while EEPROM requires byte (1 B) erase and byte (1 B) program, causing large overhead in the cell array area. The EEPROM data change size is down to the level of one single byte, much smaller than FLASH erase size. The EEPROM cell structure and program erase scheme are designed for highly reliable FN-channel erase and FN-channel program to achieve high P/E cycles. Furthermore, the data change rate of EEPROM is much higher than FLASH, thus P/E cycles of more than 500K and write speeds of less than 10 mS are strictly requirements in EEPROM. In contrast to EEPROM, today's majority of leading FLASH cells, cell operating schemes, process and its associated array architectures are neither optimized for the schemes of FN-channel erase and FN-channel program nor for meeting a byte operation product specification.
Traditional FLASH memory is less flexible than EEPROM in erase size, but 2Tr-FLOTOX EEPROM suffers a big penalty in cell size and cell array area. There are two disadvantages that cause this larger cell size and cell array area of 2Tr-FLOTOX EEPROM. One is the non-scalable cell structure due to a requirement of extremely high program voltages of 15V in the bitline. The other disadvantage is the requirement of flexible byte erase and byte program, which results in an unique area consuming cell array architecture-divided wordline and divided bitline in units of bytes. The unique byte-array organization allows EEPROM cell to perform FN-channel erase and FN-channel program for highly reliable P/E cycles without disturbing the remaining bytes either in the same selected wordline or the same selected bitlines. Since the cell structure and P/E scheme of traditional 2Tr-FLOTOX EEPROM technology is not scalable as compared with its FLASH counterpart, the highest density of EEPROM technology available in 2002 is only 1 Mb made of 0.25 um, while FLASH is 1 Gb made of 0.12 um. The density of EEPROM is about 1000 times behind FLASH in the nonvolatile market.
In conclusion, there is a strong market need for faster byte-erase and byte-program (less than 10 mS), higher P/E cycles (more than 500K) and the larger density (more than 1 Mb) at a lower manufacturing cost. e.g. A demand for low-cost FLASH-based EEPROM to offer comparable PIE cycles like EEPROM on the units of byte.
Recently, several FLASH-based EEPROM cells of prior art were disclosed claiming to have high cell scalability and highly reliable P/E cycles with the same P/E schemes of FN-channel-erase and FN-channel program. These recent prior arts intend to replace the un-shrinkable 2Tr-FLOTOX EEPROM cell and technology. Although the proposed FLASH-based EEPROM cell sizes are indeed being improved to be smaller than their FLOTOX counterparts to achieve the single-byte erase and program, the cell arrays turn out to have larger overhead than FLOTOX-array. For example, in Toshiba's disclosed 3Tr-NAND and 4Tr-NAND (as well as other prior art), the cell array is divided into a vertical triple-well for each single byte pitch. These are disclosed in Toshiba's U.S. Pat. Nos. 6,370,081 and 6,400,604. As a consequence, the total die area of Toshiba's proposed FLASH-based EEPROM still has a very large overhead. This overhead is drastically increased as the cell geometry is shrunken smaller and smaller.
Other patents disclose FLASH or EEPROM memories. These include Infineon's U.S. Pat. No. 6,307,781 to Shum, U.S. Pat No. 6,212,102 to Georgakos et al, and U.S. Pat. No. 6,266,274 to Pockrandt et al, U.S. Phillips' U.S. Pat. No. 6,174,759 to Verhaar et al and U.S. Pat. No. 6,326,661 to Dormans et al, and Aplus' U.S. Pat. No. 5,748,538 to Lee et al and co-pending U.S. patent applications Ser. Nos. 09/852,247 filed on May 9, 2001 and Ser. No. 09/891,782 filed on Jun. 27, 2001, herein incorporated by reference.